Smaller CMOS devices typically equate to faster switching times which, in turn, lead to faster and better performing end user systems. The process of miniaturizing CMOS devices involves scaling down various horizontal and vertical dimensions in the CMOS device. In particular, the thickness of the ion implanted source/drain junction of a p-type or n-type transistor is scaled down with a corresponding scaled increase in substrate channel doping. In this manner, a constant electric field is maintained in the transistor channel which typically results in higher speed performance for scaled down CMOS transistors. The formation of source/drain extension junctions in CMOS devices is typically carried out in the prior art by ion implantation in appropriately masked source/drain regions of a Si substrate with boron (p-type) or arsenic and phosphorus (n-type) dopants. Although ion implantation is used in creating the source/drain regions, ion implantation causes crystal damage to the Si substrate as well as the formation of excess Si interstitials. During subsequent thermal annealing, the presence of excess Si interstitial greatly enhances dopant diffusion (10 to 1000 times). This greatly enhanced diffusion of dopants due to the presence of excess Si interstitials around the dopant atoms is commonly referred to in the prior art as transient enhanced diffusion (TED).